Make based build System

 

What is “Make”

Make is a build automation tool that is commonly used to build and manage projects written in C and C++. It uses a file called a "makefile" that specifies how the project should be built, including the dependencies between source files and the rules for building the final executable.

How to Create a Makefile? 

To create a makefile from scratch, you will need to do the following:

1. Determine the targets that you want to build and the dependencies between them. For example, if you have a project with multiple source files, you may want to create a target for each executable that you want to build, and specify the object files that the executable depends on.

2. Define the variables that you will use in the makefile. For example, you may want to define variables for the compiler and flags that you will use to build the project.

3. Write the rules that define how the targets should be built. Each rule should specify a target, a list of dependencies, and a recipe that specifies the commands to be run to build the target.

4. Optional: include additional features such as conditional statements and recursive build rules to make your makefile more flexible and powerful.

Working Example

Let’s Say we have the following Sources in C 

main.c

#include <stdio.h> #include "hello.h" int main() {   // call a function in another file   hello();   return 0; }

hello.c

#include <stdio.h> #include "hello.h" void hello(void) {   printf("Hello makefiles!\n"); }

hello.h

#ifndef HELLO_H #define HELLO_H void hello(void); #endif

Here is an example of a makefile for this C project with multiple source files and header files

Makefile

CC=gcc CFLAGS=-I. DEPS = hello.h SRCS = main.c hello.c OBJS = $(SRCS:.c=.o) %.o: %.c $(DEPS)         $(CC) -c -o $@ $< $(CFLAGS) hellomake: $(OBJS)         $(CC) -o $@ $^ $(CFLAGS) clean:         rm -f *.o hellomake

In this makefile, the DEPS variable specifies a list of header files that are included by the source files. 

The %.o: %.c $(DEPS) rule specifies that an object file depends on both the corresponding source file and the header files listed in the DEPS variable. This ensures that the object file will be rebuilt if any of the header files are modified

Explanation (Step by Step)

Here is an explanation of each line in the makefile

CC=gcc

This line defines the CC variable as GCC, which specifies the C compiler that will be used to build the project.

CFLAGS=-I.

This line defines the CFLAGS variable as -I., which specifies a compiler flag that tells the compiler to include files from the current directory.

DEPS = hello.h

This line defines the DEPS variable as a list of header files that are included by the source files.

SRCS = main.c hellofunc.c

This line defines the SRCS variable as a list of source files.

OBJS = $(SRCS:.c=.o)

This line defines the OBJS variable as a list of object files that correspond to the source files, using a pattern substitution rule. The %.o: %.c rule specifies that an object file depends on the corresponding source file.

%.o: %.c $(DEPS)         $(CC) -c -o $@ $< $(CFLAGS)

This rule specifies that an object file depends on both the corresponding source file and the header files listed in the DEPS variable. The $(CC) variable is expanded to the value of the CC variable (gcc), and the $(CFLAGS) variable is expanded to the value of the CFLAGS variable (-I.). 

The $@ and $< variables are special variables that are expanded to the target and dependencies of the rule, respectively. This rule specifies that the object file should be built by compiling the source file with the C compiler and flags specified in the CC and CFLAGS variables

hellomake: $(OBJS)         $(CC) -o $@ $^ $(CFLAGS)

This rule specifies that the hellomake target depends on the object files listed in the OBJS variable. The $^ variable is a special variable that is expanded to the list of dependencies of the rule. This rule specifies that the hellomake executable should be built by linking the object files with the C compiler and flags specified in the CC and CFLAGS variables.

clean:         rm -f *.o hellomake

This rule defines a clean target with no dependencies. The recipe for this target specifies that all object files and the hellomake executable should be removed. This can be useful for cleaning up the build directory and starting fresh. 

Build and Cleaning of the project 

To build the project using the makefile on a Linux system, you can use the following command:

$ make hellomake

This command will invoke the make utility and pass in the name of the target you want to build (hellomake). Make will then parse the makefile, determine the dependencies between the various targets, and build them in the correct order.

If you want to clean the project and remove all object files and the hellomake executable, you can use the following command:

$ make clean

This will invoke the clean target defined in the makefile, which will remove all object files and the hellomake executable.

You can also use the -f option to specify the name of the makefile if it is not named Makefile or makefile. For example:

$ make -f mymakefile hellomake

This will use the mymakefile file as the makefile instead of the default Makefile or makefile.

All the source files of this project can be found here 

https://github.com/hassin23ayz/Make-Build-System